Close

Presenter

<
Xi Wang
Southeast University
Presentations
Late Breaking Results
Late Breaking Results: LLM-Driven Constraint Generation and Deferred Shape Exploration for Analog IC Floorplanning
6:43pm - 6:47pm PDT Monday, July 27 Exhibit Hall
Research Manuscript
Chipmodeler: LLM-Aided Reference Model Design for Agile Hardware Verification
5:18pm - 5:30pm PDT Monday, July 27 Mtg Room 101A
AI
AI1. AI/ML Frontiers for Hardware Design
Research Manuscript
Circuitdiff: Bridging Netlist Knowledge with RTL Based on Graph Denoising Diffusion
11:36am - 11:50am PDT Monday, July 27 Mtg Room 101A
AI
AI1. AI/ML Frontiers for Hardware Design
Research Manuscript
Beyond Fuzzer Islands: CPU Fuzzing via Smart Coordination
3:42pm - 3:54pm PDT Monday, July 27 Mtg Room 201B
EDA
EDA2. Design Verification and Validation
Research Manuscript
Uvmarvel: an Automated LLM-Aided UVM Machine for Subsystem-Level RTL Verification
4:06pm - 4:18pm PDT Monday, July 27 Mtg Room 201B
EDA
EDA2. Design Verification and Validation
Research Manuscript
Paretopilot: Global Optimization Reasoning on HLS Design Space Exploration with LLMs
1:55pm - 2:08pm PDT Monday, July 27 Mtg Room 101A
AI
AI2-I. AI/ML Algorithms and Models
Research Manuscript
ZK-Tracer: A High-Performance Heterogeneous Accelerator for Zero-Knowledge VM Trace Generation
3:54pm - 4:06pm PDT Wednesday, July 29 Mtg Room 203AB
Design
DES1-I. SoC, Heterogeneous, and Reconfigurable Architectures
Research Manuscript
Insights from Verification: Training a Verilog Generation LLM Using Reinforcement Learning with Testbench Feedback
11:10am - 11:23am PDT Monday, July 27 Mtg Room 201B
EDA
EDA5. RTL/Logic Level and High-level Synthesis
Research Manuscript
ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMs
3:30pm - 3:42pm PDT Monday, July 27 Mtg Room 101A
AI
AI1. AI/ML Frontiers for Hardware Design
Research Manuscript
Toward True-3D Timing-Driven Analytical Global Placement for Mixed-Size Face-to-Face 3D ICs
4:18pm - 4:30pm PDT Wednesday, July 29 Mtg Room 202AB
EDA
EDA7-I. Physical Design and Verification