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Hugo Jiang
University of Cambridge
Presentations
Research Manuscript
ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMs
3:30pm - 3:42pm PDT Monday, July 27 Mtg Room 101A
AI
AI1. AI/ML Frontiers for Hardware Design
Research Manuscript
LLMVA: LLMs Empowered Verilog-A Iterative for MRAM Design Technology Co-Optimization
1:42pm - 1:55pm PDT Tuesday, July 28 Mtg Room 101B
EDA
EDA8. Design for Manufacturability and Reliability