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Zixuan Li
Shanghai Jiao Tong University
Presentations
Work in Progress
Late Breaking Results: Analog Circuit Sizing via LLM-Guided Heuristic Search with Metric Difficulty Awareness
6:20pm - 6:21pm PDT Monday, July 27 Exhibit Hall
Research Manuscript
Chiplanner: Physically-Aware and Timing-Driven Design Planner for 2.5D Multi-Chiplet Systems
2:47pm - 3:00pm PDT Monday, July 27 Mtg Room 201B
Chiplet
EDA
EDA1. Design Methodologies for System-on-Chip and 3D/2.5D System-in-Package