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Tsung-Yi Ho
The Chinese University of Hong Kong
Presentations
Research Manuscript
Moduplace: LLM-Assisted Modular PCB Placement via Preference-Optimized Constraint Graph Generation
4:18pm - 4:30pm PDT Tuesday, July 28 Mtg Room 203AB
EDA
EDA7-II. Physical Design and Verification
Research Manuscript
Mixed-Structure Double-Sided Redistribution Layer Routing for Glass Interposer-Based 5.5D ICs
4:30pm - 4:42pm PDT Tuesday, July 28 Mtg Room 202AB
EDA
EDA7-I. Physical Design and Verification
Research Manuscript
RTL-3D: Timing-Aware Tier Partitioning for 3D ICs Using Pre-Synthesis Timing Analysis
10:56am - 11:10am PDT Monday, July 27 Mtg Room 202AB
EDA
EDA3. Timing Analysis and Optimization
Research Manuscript
Mappingevolve: LLM-Driven Code Evolution for Technology Mapping
3:30pm - 3:43pm PDT Tuesday, July 28 Mtg Room 201B
EDA
EDA5. RTL/Logic Level and High-level Synthesis
Late Breaking Results
SAT-Helper: A Multi-Agent System for Adaptive Optimizing Large-Scale Conjunctive Normal Form
5:48pm - 5:51pm PDT Monday, July 27 Exhibit Hall
Research Manuscript
BLADE: Bi-Level Bayesian Optimization for Metal-Density-Constrained Multi-Layer Package Power/ground Plane Synthesis
3:42pm - 3:54pm PDT Monday, July 27 Mtg Room 202AB
EDA
EDA4. Power Analysis and Optimization
Late Breaking Results
Late Breaking Results: "describing" Your Way to a Functional Microfluidic Chip
6:08pm - 6:11pm PDT Monday, July 27 Exhibit Hall
Research Manuscript
Diffsp: Differentiable Sequence Pair-Based Analog Placement
4:30pm - 4:42pm PDT Wednesday, July 29 Mtg Room 101B
EDA
EDA6. Analog CAD, Simulation, Verification and Test
Work in Progress
Late Breaking Results: High-Fidelity Simulation and Real-Time Forecasting of Fluid-Solute-Coupled Microfluidics
6:05pm - 6:06pm PDT Monday, July 27 Exhibit Hall
Research Manuscript
Flexicts: CPPR-Aware 3D Clock Tree Synthesis for Face-to-Face Bonded ICs
1:30pm - 1:42pm PDT Monday, July 27 Mtg Room 201B
Chiplet
EDA
EDA1. Design Methodologies for System-on-Chip and 3D/2.5D System-in-Package
Research Manuscript
BSPDN-Elite: A Comprehensive Framework for Optimizing Timing, Power and Routing Resources in BSPDN Designs
2:08pm - 2:21pm PDT Monday, July 27 Mtg Room 201B
Chiplet
EDA
EDA1. Design Methodologies for System-on-Chip and 3D/2.5D System-in-Package