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Jianli Chen
Fudan University
Presentations
Late Breaking Results
Late Breaking Results: 3D Analytical Placement with Smoothed Multi-Die Wirelength Model
6:47pm - 6:50pm PDT Monday, July 27 Exhibit Hall
Research Manuscript
Area-Optimal and Routability-Driven Layout Synthesis for Multi-Row Complementary-FET Standard Cells
3:30pm - 3:42pm PDT Tuesday, July 28 Mtg Room 203AB
EDA
EDA7-II. Physical Design and Verification
Research Manuscript
AccDRC: FPGA Acceleration for VLSI DRC with Cell-Aware Layout Partitioning
5:18pm - 5:30pm PDT Monday, July 27 Mtg Room 201B
EDA
EDA2. Design Verification and Validation
Research Manuscript
DRCGen: A Controllable DRC Violation Case Generator with Cross-PDK Transferability for Rule-Deck and Tool Validation
4:42pm - 4:54pm PDT Tuesday, July 28 Mtg Room 202AB
EDA
EDA7-I. Physical Design and Verification