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Presenter

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Jeyavijayan Rajendran
Texas A&M University
Presentations
Research Panel
Who Verifies the Verifier? Trust and Accountability in the Age of Autonomous EDA Agents
1:30pm - 3:00pm PDT Monday, July 27 Mtg Room 104A
AI
Research Manuscript
Attackonctf: Defending Hardware Security Competition Benchmarks in the Age of LLMs
4:54pm - 5:06pm PDT Tuesday, July 28 Mtg Room 203C
Security
SEC2. Hardware Security: Primitives, Architecture, Design & Test
Workshop
GREAT (gen-AI Red-Team Evaluation of Microelectronics Assurance and Trust)
9:00am - 5:00pm PDT Sunday, July 26 Mtg Room 101B
Chair of Sessions
Research Manuscript
RM Poster Session Three
5:30pm - 6:00pm PDT Monday, July 27
AI2-I. AI/ML Algorithms and Models
Design
DES4. Digital and Analog Circuits; Design
DES1-I. SoC
Heterogeneous
and Reconfigurable Architectures; EDA
EDA4. Power Analysis and Optimization; EDA
EDA2. Design Verification and Validation; Security
SEC4. Embedded and Cross-Layer Security; AI
AI1. AI/ML Frontiers for Hardware Design; AI