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Presenter

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SoYoung Kim
Sungkyunkwan University
Presentations
Engineering Poster
A Chip-Level DTCO Framework for Yield-Aware Back-End Design: Layout-Aware Misalignment Correction in DRAM
5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Work in Progress
Late Breaking Results: Die Area and Temperature Co-Optimization for Thermal Throttling Mitigation in Mobile Application Processors
5:39pm - 5:40pm PDT Monday, July 27 Exhibit Hall