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PRATEEK PENDYALA
Google
Biography
Power Delivery & Physical Design Methodology Engineer at Google
Presentations
Engineering Presentation
Correct-by-Construction Framework for Robustness Against Divergent Voltage Drops and High Clock Divergence
10:45am - 11:00am PDT Tuesday, July 28 Seaside RM 7
EDA
Security
Late Breaking Results
Hierarchical ML-Framework for Rapid RDL and Bump Optimisation in GPIO-Encroached Flip-Chip SoCs
6:53pm - 6:56pm PDT Monday, July 27 Exhibit Hall
Engineering Poster
Differential Validator: Ensuring SoC ROM to Hierarchical Blocks Node Voltage Integrity
5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems