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Qiang Xu
The Chinese University of Hong Kong
Presentations
Research Manuscript
Beyond Flat Netlist: Hierarchical Graph Representation Learning for Scalable Analysis of Sequential Circuits
10:43am - 10:56am PDT Monday, July 27 Mtg Room 101A
AI
AI1. AI/ML Frontiers for Hardware Design
Research Manuscript
Mappingevolve: LLM-Driven Code Evolution for Technology Mapping
3:30pm - 3:43pm PDT Tuesday, July 28 Mtg Room 201B
EDA
EDA5. RTL/Logic Level and High-level Synthesis
Research Manuscript
TRACE: Learning to Compute on Circuit Graphs
5:06pm - 5:18pm PDT Wednesday, July 29 Mtg Room 101A
AI
AI2-II. AI/ML Algorithms and Models
Research Manuscript
Miter-Aware LUT Mapping: Aligning Structure and Solvability for Efficient Logic Equivalence Checking
11:18am - 11:30am PDT Wednesday, July 29 Mtg Room 202AB
EDA
EDA2. Design Verification and Validation