Presentation
ML-Net: Enhanced Interconnect Modeling Through Machine Learning–based Framework and Novel Double-π Networks
DescriptionAccurate timing estimation in VLSI circuits is strongly influenced by interconnect parasitics. Current timing analysis models the distributed RC network as either Lumped-Capacitance or π model. In this work, the Double-π model is introduced as a new RC representation that captures higher-order distributed effects. Higher-order models offer more accuracy at the cost of increased computation cost. Using a single RC equivalent model for all interconnects often leads to either excessive computational cost or loss of accuracy. This work presents a machine learning–based framework that automatically and rapidly identifies the most suitable simplified RC representation—Lumped Capacitance, π, Double-π, or Distributed—for precise gate delay estimation. The framework determines the minimal RC model that maintains delay deviation within 1% of a fully distributed network. A dataset of 10,000 randomized RC networks was generated for each inverter size and timing arc to support model training and validation. Across all evaluated inverter sizes, the proposed framework achieved an average classification accuracy—based on the best-performing model per configuration—of 94% for T_p (propagation delay) and 93% for T_(rf-out)(output transition time). The proposed framework enables dynamic and optimal selection of interconnect models across a wide range of complexities and types, including both mathematical and circuit-based representations, thereby supporting accurate and scalable timing analysis for advanced VLSI design flows.
Event Type
Work in Progress
TimeMonday, July 275:15pm - 5:15pm PDT
LocationExhibit Hall