Presentation
A 1.31 TOPS/W CGRA Hardware with SIMD and Programmable Memory Address Generation Unit for Edge AI
DescriptionCoarse-Grained Reconfigurable Arrays (CGRA) offers a balance between a processor's flexibility and a domain-specific accelerator's high energy efficiency. However, conventional CGRAs typically employ some of its Processing Elements (PEs) to compute the addresses for memory access, resulting in lower hardware utilization during workload execution. In this work, we propose a CGRA featuring a dedicated Address Generation Unit (AGU) that directly generates addresses for PEs to fetch and send data, thereby achieving higher utilization. Our simulation results show that incorporating the AGU improves CGRA utilization by a factor of 2× when executing a 64x8 square General Matrix Multiplication (GeMM) workload. The proposed CGRA also supports Single-Instruction-Multiple-Data (SIMD) to accelerate operations while boosting energy efficiency up to 3.96×. Implemented in 12nm FinFET technology, our post-layout simulation demonstrates that the proposed design operates at 1 GHz and achieves an energy efficiency of 1.31TOPS/W, which is 3.4× better than the state-of-the-art.
Event Type
Work in Progress
TimeMonday, July 276:57pm - 6:58pm PDT
LocationExhibit Hall