Presentation
Generalized Structural Bias Analysis for Corrupt-and-Correct Logic Locking
DescriptionCorrupt-and-Correct (CAC) logic locking techniques offer strong resilience against Boolean satisfiability (SAT) attacks. However, the additional perturbation and correction circuitry can introduce detectable structural artifacts. Existing structural attacks and associated metrics remain narrowly scoped, limiting their effectiveness for integrated circuit (IC) designers seeking to assess structural bias. This paper formalizes a structural bias metric that tracks the polarity of all internal circuit signals and quantifies the deviation between circuit behavior under protected input patterns (PIPs) and behavior induced by random excitation. The metric can be evaluated with only a small number of tests, enabling a lightweight, design-time diagnostic that identifies gates whose bias exceeds a threshold. This approach substantially improves the generality and practical utility of structural bias assessments compared to the state of the art. The developed metric is further employed to construct a structurally aware SAT attack (StrAT) that directs the solver toward the most biased gates. Across the ISCAS'85, MCNC, and ITC'99 combinational benchmarks locked with SFLL-HD0, SFLL-flex, and SFLL-rem, StrAT succeeds in 96.5% of the cases the original attack failed to find the key in the same time window.
Event Type
Work in Progress
TimeMonday, July 276:55pm - 6:56pm PDT
LocationExhibit Hall