Presentation
Leak-CIM: A PVT-Robust and Energy-Efficient SRAM-CIM Macro Exploiting Transistor Leakage
DescriptionWe propose Leak-CIM, a PVT-robust, low-power SRAM-based analog computing-in-memory macro for edge DNN inference. A voltage-mode MAC exploits subthreshold leakage of off-state transistors as ultra-high-resistance pseudo-resistors, suppressing dynamic shoot-through current and enabling rail-to-rail operation with wide dynamic range. Post-fabrication N-well bias calibration compensates pMOS/nMOS mismatch, improving MAC linearity in 22nm bulk CMOS, reducing NMSE from 6.82% to 0.53% at the worst corner. Leak-CIM achieves 1609 TOPS/W on CIFAR-10 with a VGG-like binarized network at 87.52% accuracy.
Event Type
Work in Progress
TimeMonday, July 276:54pm - 6:55pm PDT
LocationExhibit Hall