Presentation
A Fast and Accurate Surrogate Model for Clock-Mesh Timing Analysis
DescriptionClock meshes are an essential technique in high-performance VLSI systems to minimize skew and handle On-Chip Variation (OCV) especially in nanometer technologies. However, analyzing meshes is difficult due to reconvergent paths and multi-source drivers. The industrial standard is to use SPICE simulations since static timing analysis (STA) tools can not handle mesh loops. SPICE simulations are accurate but slow, and approximate models miss critical effects like input slew and input skew. In this work, we propose a Graph Neural Network surrogate model of the clock mesh represented as a graph with augmented structural and physical features. Trained on SPICE data, our model achieves high accuracy with average delay error of 1.70ps on unseen real designs versus 87.30ps from prior approximate models, while achieving speed-ups up to 3900x over multi-threaded SPICE simulation enabling faster and accurate analysis for clock meshes. Furthermore, we demonstrate the adaptability of our model through transfer learning and use it for OCV analysis.
Event Type
Work in Progress
TimeMonday, July 276:52pm - 6:53pm PDT
LocationExhibit Hall