Presentation
ReConCHF: ReRAM-Based Reconfigurable Architecture for Cryptographic Hash Functions with Software/hardware Integration
DescriptionAs cryptographic hash functions (CHFs) continue to grow in complexity and computational demand, researchers have turned to Processing-in-Memory (PIM) architectures to alleviate the data transfer bottlenecks inherent in traditional computing. However, existing works often focus on accelerating individual operations, while overlooking full dataflow optimization and support for a wide range of CHF algorithms. Moreover, prior studies tend to emphasize hardware design but neglect the critical software interface. In this study, we propose ReConCHF, a Resistive Random-Access Memory (ReRAM)-based architecture for accelerating CHF computations. By leveraging the intrinsic in-memory capabilities of ReRAM crossbars, ReConCHF enables efficient bitwise operations critical to CHFs. With further innovations in hardware design and dataflow optimization, significant improvements in CHF performance are achieved. Additionally, we provide a reconfigurable ISA and toolchain to map software CHF descriptions to hardware. Our results demonstrate that ReConCHF achieves up to 6.7×/3.6× the throughput compared to ReVAMP SHA2/SHA3, a ReRAM-based CHF accelerator, while each Tile occupies a mere 0.0634 mm2 with a power consumption of only 118 mW.
Event Type
Work in Progress
TimeMonday, July 276:49pm - 6:50pm PDT
LocationExhibit Hall