Presentation
High Fan-in Dynamic Leakage Suppression Standard Cells for Improved Power, Performance, and Area in Ultra-Low Power Circuits Authors: Suprio Bhattacharya and Benton Highsmith Calhoun
DescriptionThis brief identifies a linear increase in the Elmore delay with fan-in size for Dynamic Leakage Suppression (DLS) logic structures, unlike quadratic increase for Static CMOS logic. We leverage this property to design high fan-in (HFI) DLS standard cells (stdcells) that improves power, performance, and area (PPA) of ultra-low power (ULP) chips for energy harvesting applications - an important domain not addressed by previous HFI works. We show important stdcell design considerations (timing, voltage swing) and PPA improvements using modeling and post-synthesis results on multiple designs (including M0+/ RISCV based SoCs) which show over 53% power, 62% delay, and 6% area reduction.
Event Type
Work in Progress
TimeMonday, July 276:46pm - 6:47pm PDT
LocationExhibit Hall