Presentation
SPEEDY: Single-Step Reinforcement Learning Framework for Efficient Analog Circuit Sizing Optimization
DescriptionReinforcement learning (RL) has shown to be promising in optimally solving the analog circuit sizing problem from simulations but often results in low sample efficiency and long execution times. We introduce SPEEDY, an actor-critic RL framework that leverages a single-step formulation to improve sample efficiency. SPEEDY accelerates convergence by running parallel, low-cost simulations that incrementally refine the design range. Evaluated on two operational transconductance amplifier topologies and a state-of-the-art low-dropout regulator design, SPEEDY achieves up to 8x of improvement in convergence time, while improving the figure of merit with respect to comparable baseline methods.
Event Type
Work in Progress
TimeMonday, July 276:45pm - 6:46pm PDT
LocationExhibit Hall