Presentation
SNN Accelerator Testing via Sparse Test Matrices
DescriptionSpiking neural network (SNN) accelerators offer the promise of energy efficiency and edge computing excellence when compared to traditional neural networks. However, they are vulnerable to faults that can cause catastrophic failures in safety-critical applications. Manufacturing defects, process variations, and malicious perturbations can alter SNN dynamics, leading to significant performance degradation. To this end, we propose a resource-optimized testing methodology for SNNs using a normalized sparse matrix, and the ensemble of Mean Absolute Membrane Potential Deviation (MAMPD) and Mean Absolute Spike Count Difference (MASCD) metrics. Our approach is founded on the key insight that hardware faults induce measurable distribution shifts in neuronal activities, deviating faulty networks from their fault-free counterparts. Experimental validation shows that our sparse test matrix approach, achieving up to 99.994% sparsity, attains 100% fault coverage under bit flips, synaptic stuck-at, and neuron faults, while reducing memory requirements by 43×, test generation time by 150K×, and computational cost by 55× compared to state-of-the-art methods.
Event Type
Work in Progress
TimeMonday, July 276:44pm - 6:45pm PDT
LocationExhibit Hall