Presentation
An Energy-Efficient Automated Hardware Generator for Edge BCI Systems
DescriptionElectroencephalography (EEG) enables non-invasive monitoring of brain activity, but its high channel count and computationally intensive neural models pose major challenges to realizing energy-efficient edge accelerator hardware for real-time brain–computer interface (BCI) systems. This work presents EEGDeep, an energy-efficient and fully automated hardware generator that bridges neural network model development and deep-learning hardware accelerators for brain–computer interface (BCI) applications. The framework integrates three core modules: an EEG channel reduction module, which prunes non-informative channels to minimize model size and computational load, enabling practical deployment in wearable applications; an EEGDeep architecture evaluator, which performs constraint-aware neural architecture and hardware exploration through model optimization, a layer-reordering algorithm, and predefined deep-learning configurations to balance accuracy, area, latency, energy, and memory bandwidth; and an EEGDeep RTL generator, which converts optimized models into synthesizable RTL using a parameterized IP template. Using this automated framework, an EEGDeep design implemented in TSMC 90-nm CMOS technology achieves a 91.67% reduction in EEG channels, a processing latency of 1.43 ms per trial, and an energy consumption of 5.51 µJ per trial. These results correspond to a 65.9% reduction in area, a 98.49% improvement in latency, a 98.6% reduction in energy consumption, and a 93.19% improvement in memory bandwidth compared with conventional implementations, demonstrating its potential for practical, low-energy, and real-time BCI applications.
Event Type
Work in Progress
TimeMonday, July 276:39pm - 6:40pm PDT
LocationExhibit Hall