Presentation
Technology-Oriented DTCO Framework Using Neural Compact Modeling and Polar Level-Set Clustering
DescriptionIn this paper, we present a process-aware Design–Technology Co-Optimization (DTCO) framework that rapidly integrates transistor-level process shifts into circuit-level Power–Performance–Area (PPA) analysis. The approach combines Neural Compact Models (NCM) with polar level-set clustering to identify and accelerate process-dependent optima within the PPA trade-off space. A semi-supervised NCM retargeting scheme reduces SPICE model development time by 98% while preserving model consistency and capturing median electrical shifts across diverse electrical targets, enabling the fast generation of technology-specific SPICE libraries and their corresponding PPA spaces. By mapping these libraries into a polar PPA domain, Pareto-based level-set clustering partitions technology behaviors into radial performance shells, laying the foundation for a radial multi-objective optimization that effectively reduces the dimensionality of subsequent design-space exploration and significantly increases the proportion of truly Pareto-optimal solutions within the elite population. This unified NCM–polar-clustering framework delivers interpretable, process-aware DTCO without TCAD or statistical sampling, and can be directly calibrated with fab data for immediate industrial deployment.
Event Type
Work in Progress
TimeMonday, July 276:38pm - 6:39pm PDT
LocationExhibit Hall
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