Presentation
Neuromorphic Ising Solver with Signed Spiking Neuron and Interleaving Simulated Annealing for Large-Scale Traveling Salesman Problem
DescriptionThe traveling salesman problem (TSP) is a fundamental combinatorial optimization problem with significant importance in various commercial and industrial domains. Numerous approaches have been proposed to address the TSP, ranging from advanced algorithmic heuristics to specialized hardware architectures, but it remains challenging to implement, especially for large-scale problems, due to the O(N^4) synaptic weight requirement and device-level constraints. In this paper, we present a scalable digital neuromorphic Ising solver that integrates 8,192 signed spiking neurons and an interleaving simulated annealing strategy on an AMD FPGA device (XC7K160T). Virtual synaptic routing, implemented through address-event-based communication, eliminates the need for fixed physical connectivity. The interleaving annealing reduces DRAM-access latency, achieving a 15% reduction in per-iteration execution time, and reduces synaptic weight storage from O(N^4) to O(N) by storing only distance-dependent coupling terms. The single-core operation provides feasible solutions for TSPLIB instances with fewer than 32 cities, while the multi-core operation parallelizes the solution of larger TSPs by partitioning the problem into hierarchical subgraphs and merging the subgraph solutions using a constraint TSP(CTSP) algorithm. With minimal per-core FPGA resource usage and a scalable architecture using virtual synaptic routing, the neuromorphic Ising solver can be expanded to hundreds of neuromorphic Ising cores.
Event Type
Work in Progress
TimeMonday, July 276:38pm - 6:38pm PDT
LocationExhibit Hall
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