Presentation
Compact ML-Based Glitch Propagation Modeling of Standard Cells
DescriptionWith continuous technology scaling, accurate and efficient glitch modeling is critical for designing energy-efficient and reliable ICs. In this work, we present a new gate-level approach for glitch propagation modeling, utilizing Artificial Neural Networks (ANNs) to estimate the key glitch shape characteristics, propagation delay, and power dissipation. Moreover, we introduce a framework that automates ANN generation and integrates them into standard cell libraries, exploring different architectures to balance accuracy and memory footprint. The proposed framework employs efficient techniques to generate realistic input glitch waveforms, reduce characterization effort, and improve model accuracy, memory efficiency, and robustness. Experimental results on gates implemented in 7 nm FinFET and 45 nm bulk CMOS technologies indicate that our models exhibit a strong correlation with SPICE, achieving a mean R2 score of 0.995 across all gates and process, voltage, and temperature corners while maintaining low memory demands. Furthermore, validation on paths extracted from real circuits confirms our models' high accuracy and performance. Thus, our approach could enable accurate full-chip glitch analysis and effectively guide glitch reduction techniques.
Event Type
Work in Progress
TimeMonday, July 276:34pm - 6:35pm PDT
LocationExhibit Hall