Presentation
Chiplite: High-Level Performance Modeling Methodology for Automotive Chiplet Systems
DescriptionAs automotive compute platforms evolve toward chiplet-based
architectures, the increasing heterogeneity introduces new challenges
in exploring the architecture design space as a function of
metrics such as performance, power, area, and cost. In this pursuit,
traditional high-fidelity methodologies, using detailed virtual
prototypes, can be cumbersome to build and computationally prohibitive
for early-stage design exploration. In contrast, analytical
techniques such as roofline modeling offer rapid insights but depend
on overly idealized assumptions — such as perfect computation–
communication overlap, and sustained peak bandwidth —
that do not hold in heterogeneous chiplet systems.
To address these limitations, we introduce ChipLite, a hybrid
modeling framework that extends the hierarchical roofline model
with workload-aware task mapping, realistic memory-access distributions,
and inter-/intra-chiplet fabric flow modeling. Using
ChipLite, we analyze three distinct chiplet architectures as example
case studies and demonstrate how workload completion times
are shaped by inter- and intra-chiplet congestion. Compared to
a naïve roofline model, for these case studies, ChipLite achieves
up to 6x lower error in predicting execution time, while retaining
orders-of-magnitude faster turnaround than detailed simulation
architectures, the increasing heterogeneity introduces new challenges
in exploring the architecture design space as a function of
metrics such as performance, power, area, and cost. In this pursuit,
traditional high-fidelity methodologies, using detailed virtual
prototypes, can be cumbersome to build and computationally prohibitive
for early-stage design exploration. In contrast, analytical
techniques such as roofline modeling offer rapid insights but depend
on overly idealized assumptions — such as perfect computation–
communication overlap, and sustained peak bandwidth —
that do not hold in heterogeneous chiplet systems.
To address these limitations, we introduce ChipLite, a hybrid
modeling framework that extends the hierarchical roofline model
with workload-aware task mapping, realistic memory-access distributions,
and inter-/intra-chiplet fabric flow modeling. Using
ChipLite, we analyze three distinct chiplet architectures as example
case studies and demonstrate how workload completion times
are shaped by inter- and intra-chiplet congestion. Compared to
a naïve roofline model, for these case studies, ChipLite achieves
up to 6x lower error in predicting execution time, while retaining
orders-of-magnitude faster turnaround than detailed simulation
Event Type
Work in Progress
TimeMonday, July 276:31pm - 6:32pm PDT
LocationExhibit Hall