Presentation
Accelerating Functional Fault Grading for Flash and DRAM Designs
DescriptionFunctional fault grading is essential for post-silicon validation in scan-limited designs, but simulation cost grows with fault and pattern volume. We propose an optimization-driven methodology combining static fault optimization, fault clustering, design pruning, stimulus grading, dynamic fault optimization, and parallel fault simulation management. By leveraging both structural design information and stimulus behavior, the flow eliminates redundant computation by performing optimized simulations tailored to fault activation and propagation potential. Applied to a production-grade NAND Flash and DRAM designs, the approach achieved a 3.7x and 2x reduction in simulation time, respectively, while preserving test coverage. The methodology is broadly applicable to logic and SoC designs, offering scalable fault grading without reliance on scan structures.
Event Type
Work in Progress
TimeMonday, July 276:30pm - 6:31pm PDT
LocationExhibit Hall
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