Presentation
Lockroute: A Spatial Locking Framework for Parallel Global Routing
DescriptionGlobal routing is a crucial step in VLSI design that has become increasingly more complex as chip sizes and design scales grow. Many global routers divide the process into several stages: two-pin decomposition, congestion map generation, maze routing and layer assignment. Each of these stages requires routing thousands to millions of nets providing opportunities for parallelization. In this paper, we demonstrate that global routing is not embarrassingly parallel and describe a lock-based approach to shared-memory parallel global routing by identifying net dependencies through the use of an R-tree. This lock framework is flexible enough to be applied to every stage of the global routing pipeline. We evaluate our global router on the ISPD 2008 and ISPD 2019 global routing contest benchmark suites. Our approach achieves a significant speedup in runtime without a reduction in quality.
Event Type
Work in Progress
TimeMonday, July 276:29pm - 6:30pm PDT
LocationExhibit Hall