Presentation
Late Breaking Results: FeMFET Multi-Level Cell Capacity Limits for SNN-Based Compute-in-Memory Inference
DescriptionFeMFET multi-level cell (MLC) operation promises high-density weight storage for spiking neural network (SNN) inference in compute-in-memory (CIM) systems. We characterise 60 FeMFET devices and show that 4-state operation produces an S2-S3 threshold-voltage separation of only 1.12 sigma (21.5% read error), rendering 4-state weights information-theoretically insufficient for reliable classification regardless of training method. Using an information-theoretic bit-budget framework, we derive BB_min ≈ 6.64 bits as the minimum information capacity for 99%-accurate 4-class inference. We validate the framework on a synthetic 4-class IR fall-detection task: weight precision of 4 bits or higher consistently exceeds the bound and achieves 96-99% accuracy under post-training quantization, while 1-bit precision collapses to chance (25%) regardless of timesteps. 3-state FeMFET operation (separation ≥ 3.35 sigma, read error probability = 0.001) achieves 74.9% under post-training quantization, whereas 4-state (read error probability = 0.215) degrades to 43.2% ± 10.6% under physical device noise. The framework translates directly into a hardware specification, providing a principled pre-training viability criterion for any CIM system with characterised device distributions.
Event Type
Work in Progress
TimeMonday, July 275:18pm - 5:18pm PDT
LocationExhibit Hall
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