Presentation
Agentic AI for Chip Design and Verification: Results and Limitations from CVDP
DescriptionWe benchmark a new agentic AI approach for chip design and verification on the CVDP dataset. Our results show that multi-agent orchestration, custom system prompts, and improved tool-use guidance enable our agent to debug and complete substantially more complex hardware verification problems. On relevant CVDP problems, our agent demonstrates a relative advantage of 11.6% vs. CVDP state of the art performance and 15.3% vs. Claude Code. Beyond aggregate metrics, we analyze execution traces and find evidence of enhanced reasoning and debugging capabilities, as well as important limitations of under- and over-specified test harnesses.
Event Type
Work in Progress
TimeMonday, July 275:13pm - 5:14pm PDT
LocationExhibit Hall