Presentation
Late Breaking Results: Fast Energy-Aware Neural Network Modeling for Efficient FPGA-Based Inference
DescriptionFPGAs provide customizable hardware acceleration that enables efficient, low-latency execution of machine learning inference through application-specific parallelism. While resource utilization and latency can typically be estimated early in the design process, accurate power consumption analysis generally requires completing the full hardware design flow, which may take several hours. In this paper, we present a framework that rapidly identifies high-quality, energy-efficient FPGA designs without requiring full compilation. The proposed approach converges to an optimal design point within seconds, achieving up to a 1000$\times$ speedup compared to conventional methods.
Event Type
Work in Progress
TimeMonday, July 275:37pm - 5:38pm PDT
LocationExhibit Hall