Presentation
Late Breaking Results: Synthesizable 8-Bit Digital Memristor Emulator with Programmable State Retention for Accelerated Edge Computing
DescriptionMemristive devices are promising for neuromorphic and in-memory computing, but practical analog implementations often face variability and fabrication challenges. This work presents a synthesizable 8-bit digital memristor emulator implemented in Verilog and targeted for FPGA realization. The design employs a discrete-time, threshold-based state update mechanism with Q1.15 fixed-point arithmetic at 10~kHz sampling. Simulation results demonstrate frequency-dependent pinched hysteresis consistent with memristive behavior, as well as programmable SET/RESET resistance modulation and stable non-volatile retention under zero excitation. The bounded 8-bit state ensures deterministic operation suitable for hardware deployment. The proposed architecture provides a compact and reproducible digital platform for architectural exploration of memristor-inspired computing systems, with scalability toward FPGA-based arrays for neuromorphic and edge computing applications.
Event Type
Work in Progress
TimeMonday, July 276:13pm - 6:13pm PDT
LocationExhibit Hall