Presentation
Late Breaking Results: Die Area and Temperature Co-Optimization for Thermal Throttling Mitigation in Mobile Application Processors
DescriptionTo mitigate workload-driven thermal throttling, advanced mobile packages adopt heat escape structures, which can bias the memory interface to one die side and significantly tighten the trade-off between thermally-constrained performance and interconnect length. We formulate thermal throttling-aware floorplanning that jointly optimizes die area, peak temperature, and xPU-to-memory-interface wirelength under such structure-induced asymmetry. We construct Pareto fronts via spatio-thermal co-exploration and extract a knee point to produce an actionable budgeting rule: a modest +10% area margin yields a −6.7°C peak temperature reduction with only +4.7% wirelength overhead, effectively guiding early-stage floorplanning.
Event Type
Work in Progress
TimeMonday, July 275:39pm - 5:40pm PDT
LocationExhibit Hall
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