Presentation
Late Breaking Results: Analog Circuit Sizing Optimization Using Procrustes-Guided Machine Learning Heuristics
DescriptionAutomated chip design techniques are commonplace in digital IC design. Hardware description languages and register-transfer logic (RTL) code allow a design to be abstracted beyond a specific process. However, analog circuit performance is inherently tied to the specific technology and tradeoffs made during the design process. Developments in machine and reinforcement learning show promise for automating the analog design process, though these algorithms require an objective function to optimize. In this work, we demonstrate the use of Procrustes distance as an analog circuit sizing heuristic suitable for machine learning optimization,
sizing an actively-loaded differential amplifier with a constant-gm bias circuit in an open-source 130 nm process, achieving over 60% increase in unity gain frequency over a manually-sized benchmark.
sizing an actively-loaded differential amplifier with a constant-gm bias circuit in an open-source 130 nm process, achieving over 60% increase in unity gain frequency over a manually-sized benchmark.
Event Type
Work in Progress
TimeMonday, July 275:34pm - 5:35pm PDT
LocationExhibit Hall