Presentation
Split–and–sync Bayesian Learning–driven SRAM Compiler: Automatic Design Tuning with Optimal Banking
DescriptionWe propose a Split-and-Sync Bayesian learning framework for SRAM compiler optimization under macro-level timing and power constraints. The framework decomposes these global constraints into leaf-cell-level objectives, where each leaf cell—such as a controller, decoder, or peripheral unit—is locally optimized through constraint-aware tuning. Our flow directly adjusts transistor-level parameters—widths and threshold voltages—and automatically regenerates the schematic and layout for each candidate. A bank-adaptive search jointly explores single- and multi-bank organizations, overcoming fixed banking rules. Implemented in a 28nm SRAM compiler, the method achieves 6.87%-15.8% in dynamic power reduction, 25.07%-26.45% access speed improvement, and a 4.5× reduction in total optimization cost.
Event Type
Work in Progress
TimeMonday, July 275:52pm - 5:53pm PDT
LocationExhibit Hall