Presentation
Hierarchical Learning–based Digital Circuit Design Tuning Framework for Power-Delay Optimization
DescriptionWe present a learning-based transistor-level design optimization framework for digital logic circuits that fully regenerates schematics and layouts after synthesis or place-and-route. Unlike conventional gate-level optimization limited to fixed standard-cell variants, it directly tunes transistor parameters. Bayesian learning with physics-guided regression refines delay and power characteristics, while a layout-in-the-loop engine ensures DRC-clean results through probabilistic search and geometric sampling. To enable fast convergence, the framework adopts a hierarchical structure that synchronizes local optimizations with global updates. Across multiplier, divider, and adder-tree circuits, it achieves up to 12% dynamic-power reduction and 5–10% delay improvement within 28–52 hours using four-core parallelism.
Event Type
Work in Progress
TimeMonday, July 275:35pm - 5:36pm PDT
LocationExhibit Hall
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