Presentation
Linearly Scalable Algorithms for DFT Static Verification, Coverage Analysis, and Debug at RTL
DescriptionIn this paper, we present DFT static verification and debug as a powerful methodology that is scalable to designs with billions of gates. The proposed methodology avoids the pitfalls of alternative approaches such as simulation, formal verification, and language learning models (LLMs) and complements the design sign-off flow. We highlight four important DFT verification problems, viz., sequential depth, scan isolation, DFT connectivity checking, and early RTL fault coverage analysis. Each problem comes with different pitfalls in existing methodology which prevents arbitrary scaling in design size. We present efficient and scalable static algorithms that scale linearly with the size of the design graph (O(V+E) in the worst case, where V is the number of gates/instances and E is the number of point-to-point nets connecting the instances). We also present results on large scale (100+ million gates) industrial designs from mobile SoC and AI/Edge application domains.
Event Type
Work in Progress
TimeMonday, July 275:14pm - 5:15pm PDT
LocationExhibit Hall