Presentation
R5-Link : Enhancing RISC-V Multi-Core Efficiency with Hardware Message Passing Channels in a 2D Mesh Network
DescriptionEfficient inter-core communication (ICC) is vital for performance and scalability in multi-core systems. We present R5-Link (RISC-V Link), a hardware–software co-designed ICC mechanism enabling low-latency, contention-free message passing across a 2D mesh network. Unlike traditional shared-memory or scratchpad-based methods, R5-Link uses dedicated bi-directional hardware queues and lightweight MPI-compatible APIs for direct neighbor-to-neighbor data exchange. This design eliminates complex synchronization and memory contention, improving communication efficiency without interfering with core execution. Implemented on a PULP RISC-V SoC (16 nm FinFET), R5-Link achieves 6.6–14.8× lower latency and 6.6–41× higher throughput compared to software-based MPI communication.
Event Type
Work in Progress
TimeMonday, July 275:33pm - 5:33pm PDT
LocationExhibit Hall
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