Presentation
An Autonomous Design Agent of Parallel Feedforward Equalizer for Advanced Wireline Receivers
DescriptionFeedforward equalizers (FFEs) are critical digital signal processing (DSP) components in ultra-high speed wireline receivers, frequently limiting power and area efficiency while requiring extensive design effort. This work introduces an autonomous design agent that automatically generates FFEs from system specifications to Verilog implementation. The framework employs a computational data-flow graph model combining unfolding and fast FIR algorithm, along with nonlinear programming for architecture to circuit level optimization. A 128-parallel, 24-tap FFE for a 112-Gbps PAM-4 receiver is successfully synthesized in TSMC 28-nm CMOS within 6 hours using the design agent, achieving 14 % power and 25 % area savings.
Event Type
Work in Progress
TimeMonday, July 275:07pm - 5:08pm PDT
LocationExhibit Hall