Presentation
Toward Agentic Solutions for DRC Challenges in Digital VLSI Design
DescriptionAs technology nodes shrink, design rule checks established by foundries to ensure manufacturability have become more complex and stringent. As a result, fixing design rule violations (DRV) in layouts has become very time-consuming and complex. In practice, DRV fixing is still performed manually during late design closure and often under intense tapeout pressure. Since DRC reports provide only limited information, such as rule names and DRV locations in layout, engineers are forced to repeatedly cross-reference reports, layouts, and lengthy design rule manuals (DRMs) to identify the cause of DRVs. Recently, large language models (LLM) have shown a strong ability to interpret rule constraints. To further drive their use for DRC-related tasks, we introduce a multimodal benchmark suite that serves as both a training dataset and an evaluation benchmark for LLM-driven workflows in DRC research. The suite pairs raw GDSII layouts and PNG screenshots with an extraction pipeline that converts GDSII into layout scripts, for open-source tools such as KLayout, making the inputs compatible with LLMs. It also provides compressed DRC annotations in JSON format that record the rule name and the corresponding DRV location, as well as compressed multimodal information derived from the DRM, including images and textual data. The benchmark includes cases from standard cell layouts to blocklevel designs built from open-source flows, including designs from OpenROAD and OpenCores synthesized using various technologies. The benchmark will enable reproducible evaluation across DRC tasks, including identifying DRVs, explaining their root causes in the layout, and fixing DRVs.
Event Type
Research Special Session
TimeMonday, July 275:00pm - 5:30pm PDT
LocationMtg Room 201A
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