Presentation
LLM for EDA in Front-End Design: Challenges and Opportunities
DescriptionThe growing complexity of modern integrated circuits has significantly increased the demands placed on hardware engineers, particularly within design, simulation, and verification workflows. These processes are inherently iterative and often rely on extensive manual effort, making them time-consuming and prone to errors. Consequently, there is an increasing need for more efficient and scalable Electronic Design Automation (EDA) solutions. Large Language Models (LLMs), which are trained on extensive human knowledge and interact naturally through text, present a promising opportunity to support front-end EDA tasks. By assisting with design generation and verification, LLMs have the potential to substantially improve circuit design productivity. In this talk, we demonstrate how LLMs can automate critical stages of the hardware development lifecycle. We introduce methods for automatically generating circuit designs and their corresponding testbenches from a shared specification, and we illustrate how LLMs can enhance design quality in established workflows such as high-level synthesis. Finally, we discuss the current challenges and limitations of LLM integration in EDA and outline future research opportunities for advancing LLM-enabled front-end design.
Event Type
Research Special Session
TimeMonday, July 274:30pm - 5:00pm PDT
LocationMtg Room 201A