Presentation
PANDA: An LLM-Enhanced Performance-Driven Analog Design Framework Bridging Design Intent and Layout Generation
DescriptionThe design of analog circuits traditionally relies on manual interventions in topology synthesis, transistor sizing, and layout generation. In this work, we introduce PANDA, a performance-driven framework that leverages large language models (LLMs) to automate the analog design flow, bridging the gap between high-level design intent and final layout. PANDA incorporates cutting-edge techniques, including LLM-empowered topology synthesis, post-layout simulation-driven sizing, and layout generation. The layout generation process is driven by an LLM-based task-decomposition engine that translates high-level design intents into precise placement and routing actions. While the underlying P\&R kernel leveraging engines such as SAGERoute—honors geometric and electrical constriants, the LLM selects constraints, steers optimization, and adaptively refines the layout, shifting the flow from algorithm-centric execution to intent-centric design. Rather than merely automating routine steps, the integration of LLMs enables PANDA to internalize design principles, infer strategy-level decisions, and generate execution-ready design directives, effectively elevating automation from procedural assistance to informed, high-level co-design. Experiments demonstrate that PANDA significantly improves design performance while reducing time and effort in producing high-quality analog layouts.
Event Type
Research Special Session
TimeMonday, July 2712:00pm - 12:30pm PDT
LocationMtg Room 201A