Presentation
Jsplace: A Shape-Controllable and Length-Matching Placement for Rapid Single-Flux-Quantum Circuits
DescriptionSuperconducting Rapid Single Flux Quantum (RSFQ) logic is a promising candidate for high-performance computing due to its ultra-high speed and ultra-low power. Since most RSFQ logic gates require synchronization with a single clock pulse, RSFQ circuits have a clock-driven gate-level pipelined architecture in nature. However, the gate-level pipelined architecture leads to layouts with a high width-to-height ratio, especially in large circuits, because the layout width increases with the number of logic stages while the height is determined by the tallest column. To address this, we propose JSPlace, a shape-controllable and length-matching placement algorithm for RSFQ circuits. Our algorithm folds the multi-stage pipelined placement into three segments and merges columns via mixed-integer linear programming (MILP) to achieve the target width-to-height ratio. Subsequently, dynamic programming determines the vertical positions of nodes within each column, followed by connectivity-driven repositioning to minimize total vertical wirelength. Experimental results on ISCAS85 and EPFL benchmarks demonstrate that JSPlace achieves effective control of layout width-to-height ratio while significantly outperforming the state-of-the-art in layout area and wirelength.
Event Type
Research Manuscript
TimeMonday, July 2710:56am - 11:10am PDT
LocationMtg Room 202C