Presentation
Sparsity- and Tolerance-Aware Temporally Redundant Neural Networks
DescriptionRecent progress in satellite formation flight in Low Earth Orbit (LEO) is driving demand for energy-efficient AI accelerators with strong soft-error resilience. This paper proposes a co-design of a fault-tolerant neural network and hardware that combines tolerance-aware temporal redundancy with sparse outer-product computation. A theoretical bound on single-bit-flip effects in residual-quantized dot products enables selective protection of only the most vulnerable computations. In addition, a zero-skip outer-product unit exploits activation sparsity created by residual quantization to reduce redundancy overhead. Implementation results show that the proposed design achieves a 16.0% speedup over the non-fault-tolerant model while keeping area overhead to 0.20–1.26%.
Event Type
Research Manuscript
TimeMonday, July 272:08pm - 2:21pm PDT
LocationMtg Room 101B
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