Presentation
Unlocking Automated Datapath Gating via Machine Learning Power Prediction
DescriptionClock gating and data gating are established techniques for reducing dynamic power. However, performing automated data gating during logic synthesis remains challenging due to the difficulty of accurately estimating power savings and identifying common Observability Don't Care (ODC) conditions for the enable logic. This work introduces a novel methodology that addresses both challenges: it introduces a novel SAT-based technique to compute valid ODC conditions and employs a machine learning-based power model to predict power improvements with high accuracy. The approach is integrated into an industrial synthesis flow and achieves efficient, fully automated, data gating. Experimental results demonstrate an average dynamic power reduction of -1% post place & route,
with negligible area and runtime overhead.
with negligible area and runtime overhead.
Event Type
Research Manuscript
TimeMonday, July 2711:23am - 11:36am PDT
LocationMtg Room 201B