Presentation
A Boolean Processor-Based Hardware Emulation System with Reconfigurable Interconnects
DescriptionExisting Boolean processor-based (BP-based) hardware emulation systems typically rely on fixed interconnects, which often suffer from severe bandwidth underutilization under highly imbalanced traffic. We propose a BP-based hardware emulation system with hierarchical reconfigurable interconnects. At both the inter-chip and intra-chip levels, our system dynamically reallocates idle interconnect lanes from low-traffic pairs to high-demand pairs, alleviating communication bottlenecks and improving interconnect utilization without modifying the underlying ASIC fabric. The hardware is co-designed with the compiler, which profiles communication, generates per-lane configuration tables and scheduling strategies, and programs the interconnect via registers. Experimental results on industrial digital designs show up to 64% emulation performance improvement and an average 27% reduction in compilation time, with only 7.4% area overhead compared to a fixed-interconnect baseline system.
Event Type
Research Manuscript
TimeMonday, July 274:42pm - 4:54pm PDT
LocationMtg Room 201B
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