Presentation
Shared Logic Unleashed: Multiple-Node Boolean Optimization for Next-Gen Synthesis
DescriptionWe present a high-effort Boolean optimization framework that restructures multiple nodes in combinational logic simultaneously, enabling area reductions beyond the reach of conventional single-output transformations. Our method generalizes Boolean resubstitution on both nodes and edges to operate across shared logic while leveraging don't-care conditions. Our approach supports coordinated removal and resynthesis of shared logic regions and expands the optimization scope to multiple-output windows. When deployed in an industrial standard-cell design flow, our framework achieves up to 6.79% area reduction and 7.85% switching power reduction post-synthesis. Additionally, it establishes 19 new best results in the EPFL synthesis competition on LUT networks.
Event Type
Research Manuscript
TimeTuesday, July 284:36pm - 4:50pm PDT
LocationMtg Room 201B