Presentation
Train Once, Calibrate Always: Machine-Learning-Assisted Blind Calibration for Analog-to-Digital Converters
DescriptionThis work introduces a machine-learning (ML)-based calibration
framework for analog-to-digital converters (ADCs) that is demon-
strated on an over-sampled, time-interleaved band-pass delta-sigma
ADC (TI-BPADC) test-chip in 65nm and a nyquist, successive ap-
proximation register (SAR) ADC test-chip in 28 nm. The proposed
framework employs two models: a hybrid convolutional-recurrent
network (ConvRec) and a residual convolutional network (ResConv)
for suppressing both static and dynamic errors in ADCs, and presents
trade-offs between the two models in terms of calibration accu-
racy and hardware cost. The proposed models improve signal-to-
noise-and-distortion ratio (SNDR) and spurious-free-dynamic range
(SFDR) by more than 20 dB on the ADC test chips without requir-
ing prior knowledge of circuit architecture, error mechanism or
input statistics. This is in contrast to existing calibration techniques
which are either algorithmic and require prior knowledge of errors
for calibration, or leverage ML for calibration but need knowledge
of input statistics. Input and error agnostic property of the proposed
ML framework is the key differentiation of this work over others
and allows correction of errors, including errors that are unforeseen
during design time.
framework for analog-to-digital converters (ADCs) that is demon-
strated on an over-sampled, time-interleaved band-pass delta-sigma
ADC (TI-BPADC) test-chip in 65nm and a nyquist, successive ap-
proximation register (SAR) ADC test-chip in 28 nm. The proposed
framework employs two models: a hybrid convolutional-recurrent
network (ConvRec) and a residual convolutional network (ResConv)
for suppressing both static and dynamic errors in ADCs, and presents
trade-offs between the two models in terms of calibration accu-
racy and hardware cost. The proposed models improve signal-to-
noise-and-distortion ratio (SNDR) and spurious-free-dynamic range
(SFDR) by more than 20 dB on the ADC test chips without requir-
ing prior knowledge of circuit architecture, error mechanism or
input statistics. This is in contrast to existing calibration techniques
which are either algorithmic and require prior knowledge of errors
for calibration, or leverage ML for calibration but need knowledge
of input statistics. Input and error agnostic property of the proposed
ML framework is the key differentiation of this work over others
and allows correction of errors, including errors that are unforeseen
during design time.
Event Type
Research Manuscript
TimeMonday, July 274:54pm - 5:06pm PDT
LocationMtg Room 203AB
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