Presentation
REPAIR: Reliability Enhancement of NVM FPGAs Through Lifetime-Aware Differential Partial Reconfiguration
DescriptionNon-Volatile Memory (NVM)-based Field Programmable Gate Ar- rays (FPGAs) have attracted attention due to lower power consump- tion, higher logic density, and instant-on capability from retained configuration data. However, NVM cells have limited write en- durance and higher latency than SRAM, which can affect long-term reliability, especially under frequent Partial reconfiguration (PR). Although PR improves design efficiency by updating only part of the logic, it imposes lifetime limitations, particularly on NVM-based Look Up Tables (LUTs).
In this paper, we introduce REPAIR, a framework that minimizes LUT reconfiguration through PR without changing the normal CAD flow. REPAIR uses a lifetime-aware fixed placement technique in the Preprocessing stage to reduce LUT reconfigurations. Moreover, it includes a postprocessing tool that generates differential partial bit- streams, writing only the changed LUT configuration bits between consecutive configurations. Finally, at runtime it incorporates a low-overhead scheduler to optimize LUT updates within the recon- figuration path. Together, these mechanisms reduce write stress on NVM cells, enhance the lifetime and reliability of Non-Volatile FPGAs (NVFPGAs) while preserving the performance and flexibility benefits of PR. Our experimental results show that REPAIR extends the operational lifetime of NVFPGAs by at least 7× compared to a baseline PR using commercial tools
In this paper, we introduce REPAIR, a framework that minimizes LUT reconfiguration through PR without changing the normal CAD flow. REPAIR uses a lifetime-aware fixed placement technique in the Preprocessing stage to reduce LUT reconfigurations. Moreover, it includes a postprocessing tool that generates differential partial bit- streams, writing only the changed LUT configuration bits between consecutive configurations. Finally, at runtime it incorporates a low-overhead scheduler to optimize LUT updates within the recon- figuration path. Together, these mechanisms reduce write stress on NVM cells, enhance the lifetime and reliability of Non-Volatile FPGAs (NVFPGAs) while preserving the performance and flexibility benefits of PR. Our experimental results show that REPAIR extends the operational lifetime of NVFPGAs by at least 7× compared to a baseline PR using commercial tools
Event Type
Research Manuscript
TimeMonday, July 2712:03pm - 12:16pm PDT
LocationMtg Room 203AB