Presentation
Pangaea: A Unified Memory-Efficient Accelerator for Pangenome Chaining and Alignment
DescriptionPangenome graphs have emerged as the new standard for genomic reference, replacing linear references to capture population-level genetic variation. However, sequence-to-graph mapping tools exhibit severe memory bottlenecks, with intermediate data movement between computation stages consuming up to 86\% of total DRAM bandwidth. Through systematic profiling of state-of-the-art tools, we identify that no single computational stage dominates across different implementations, necessitating cross-stage optimization approaches rather than accelerating individual kernels.
We present PANGAEA, a co-design framework that formulates cross-stage loop fusion as an optimization problem to minimize DRAM traffic under on-chip buffer constraints. Our approach fuses the three memory-intensive stages (i.e., linear chaining, graph chaining, and wavefront alignment). The framework automatically generates tiling parameters and scheduling schemes that maximize data reuse across genome analysis kernels with different dependency patterns. We design PANGAEA accelerator with a unified tri-mode processing element array supporting sparse chaining and dense alignment operations. Compared to SOTA ASIC implementations, \name achieves an average of 1.47$\times$ higher throughput (bp/s), 1.73$\times$ better energy efficiency($\text{bp}/\mu\text{J}$) and 1.62$\times$ area efficiency(bp/s/mm$^2$).
We present PANGAEA, a co-design framework that formulates cross-stage loop fusion as an optimization problem to minimize DRAM traffic under on-chip buffer constraints. Our approach fuses the three memory-intensive stages (i.e., linear chaining, graph chaining, and wavefront alignment). The framework automatically generates tiling parameters and scheduling schemes that maximize data reuse across genome analysis kernels with different dependency patterns. We design PANGAEA accelerator with a unified tri-mode processing element array supporting sparse chaining and dense alignment operations. Compared to SOTA ASIC implementations, \name achieves an average of 1.47$\times$ higher throughput (bp/s), 1.73$\times$ better energy efficiency($\text{bp}/\mu\text{J}$) and 1.62$\times$ area efficiency(bp/s/mm$^2$).
Event Type
Research Manuscript
TimeTuesday, July 282:21pm - 2:34pm PDT
LocationMtg Room 202C