Presentation
Learning the "why": Causal-Aware Learning in Explainable and Efficient CPU Design Optimization
DescriptionAs modern CPUs grow increasingly configurable, design space exploration (DSE) has become essential for navigating complex architectural trade-offs. However, existing DSE approaches predominantly rely on statistical correlations, resulting in opaque decision processes. They cannot clearly explain the underlying causes of how configurations affect PPA outcomes, which in turn reduces designers' confidence in automated recommendations. To address this limitation, we introduce causal learning into the DSE pipeline and develop CAL-DSE, a framework that constructs a validated causal graph combining statistical evidence with LLM-informed domain knowledge. Building on this structure, the causal graph decomposes the high-dimensional design space, enabling both interpretability and efficient exploration. Experimental results on RISC-V processor show that CAL-DSE achieves up to 4.12× hypervolume improvement while revealing validated causal pathways between design parameters and PPA outcomes.
Event Type
Research Manuscript
TimeTuesday, July 2810:56am - 11:10am PDT
LocationMtg Room 101B