Presentation
Memflow: Characterizing Memory Traffic Contention in Disaggregated Architectures
DescriptionScale-up networks support memory semantics between pooled, disaggregated processor and memories; meanwhile, it triggers complex any-processor-to-any-memory accesses and creates intricate contention of micro-architectural components. Nevertheless, existing simulators fail to adequately characterize the interference due to oversimplified memory access paths. This paper presents the MemFlow simulator. MemFlow features a modular, fine-grained hardware abstraction of disaggregated memory systems, provides a flow-centric simulation scheme to trace the complete memory access path from load-store queues through cache hierarchies to memory controllers, evaluates micro-architectural contention with detail and fidelity, and enables automatic design space exploration to mitigate contention-induce performance degradation.
Event Type
Research Manuscript
TimeTuesday, July 283:42pm - 3:54pm PDT
LocationMtg Room 202C