Presentation
Tsetlinwisard: On-Chip Training of Weightless Neural Networks Using Tsetlin Automata on FPGAs
DescriptionThe growing need for environmental adaptability, privacy, and security in edge applications drives the search for alternatives to deep learning that are both computationally efficient and hardware-friendly. WiSARD Weightless Neural Networks (WNNs) meet this need through simple table lookups, offering low latency and minimal computation. In this work, we propose TsetlinWiSARD, an FPGA-based on-chip training architecture for WiSARD WNNs that leverages Tsetlin Automata (TAs) to enable probabilistic, feedback-driven learning. By mapping logical LUTs and TAs onto physical LUTs on FPGAs, TsetlinWiSARD achieves state-of-the-art accuracy, over 1000× faster training, and reduced resource use (22%), latency (93.3%), and power (64.2%).
Event Type
Research Manuscript
TimeTuesday, July 284:42pm - 4:54pm PDT
LocationMtg Room 202C
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